As semiconductor devices have trended towards higher speeds and larger scale integration, metal interconnections formed in semiconductor devices have sub-micron feature sizes and a multi-layer structure. As the width of metal interconnections is narrowed, an increased signal delay is generated due to the increased resistance or capacitance of the metal interconnections. Thus, copper interconnections, which have a relatively low resistance, have been used to reduce such signal delay.
Since copper is not as easily etched as compared with aluminum, for example, a trench is formed to properly shape a copper interconnection. A copper layer is deposited to fill the trench, and then a damascene process including the chemical and mechanical polishing (CMP) is performed, thereby forming the copper interconnection.
However, a diffusion barrier must be formed between the copper interconnection and an insulating layer due to the propensity of copper to diffuse into other layers. A diffusion barrier should adhere well to both the copper layer and an interlayer dielectric layer. It should also possess excellent EM (electro migration) and SM (stress induced migration) properties.
However, most diffusion barriers have a shortcoming. The diffusion barriers with good EM properties have poor SM properties, and diffusion barriers having good SM properties have poor EM properties.
In particular, the SM property may be deteriorated by a difference in the thermal expansion coefficients between the diffusion barrier and the copper or between the diffusion barrier and the insulating layer, and a void may be generated.
Such a void may interrupt the signal transmission in the copper interconnection, thereby reducing reliability of the device.